


module cbb_rom #(
    parameter MEM_FILE = "rom.hex",  // ROM初始化文件 
    parameter MEM_NUM  = 256 ,// ROM存储的数量
    parameter DATA_WIDTH = 8 , //数据位宽
    parameter ENABLE_ASYNC = 0  // 是否异步于时钟输出
)(
    input clk , 
    input  [$clog2(MEM_NUM-1) - 1 :0]   address,
    output [DATA_WIDTH-1:0] data_out 
);

(* ram_style = "block" *)
reg [DATA_WIDTH-1 : 0] mem [0 : MEM_NUM-1] /* synthesis syn_ramstyle = "block_ram" */; 


initial begin 
    if(|MEM_FILE) begin 
        $readmemh(MEM_FILE , mem ) ; 
        $display("Preloading %m from %s", MEM_FILE);
    end  else begin
        $display("No init memfile");
    end 
end 


reg [DATA_WIDTH - 1 : 0 ]data_out_r; 
generate
    if(ENABLE_ASYNC==0) begin : sync_out
        always@(posedge clk) begin
            data_out_r <= mem[address] ;
        end
    end else begin : async 
        always@(*) begin
            data_out_r = mem[address] ;
        end
    end 

endgenerate

assign data_out  = data_out_r ;

endmodule 
